Contact Info:
Summary
Intimate knowledge of and experience with high-speed digital design for data communication and consumer electronics. Experienced producing designs meeting Telecordia NEBS, UL, CSA, CE requirements. Skilled in the design and programming of embedded systems from inception to full production.
Skills:
C, AC, Assembly for ARM, 860/750 PowerPC architecture, many different microcontrollers, Verilog, VHDL PCI/PCIe/UTOPIA/POS PHY/SFI Interfaces, Cadence Allegro PCB and PCB SI, Cadence Design HDL, Cadence Capture CIS, Mentor PowerPCB, DxDesigner, Hyperlynx, Xilinx, Altera
Work Experience:
2008 - PRESENT JDSU, Inc morrisville, NC
SENIOR R&D Engineer, SOLUTIONS BUSINESS UNIT
Design new and maintain existing communication test products for video probes, ethernet backhaul probes, and remote cellular service probes.
Accomplishments include:
- Completion an auxiliary mobile platform (AMP) that allows for integration of cellular handsets and data devices into the a cellular test probe. This allowed testing of leading edge cellular services using the first available products rather than waiting for release of compatible embedded cellular modules.
- Mechanical and electrical designs for including several different cellular devices in the AMP product.
- Managing FCC permissive change documentation and testing for these products, as well as safety and EMC testing.
- Maintaining current Remote Cellular Acess Test Probes (RCATS).
- Architecture and planning for a next generation remote cellular probes.
- Architecture and design of a 1GIG Ethernet/ASI/SMPTE interface for video test probes. Managed EMC and safety testing of updated product.
- Maintenance and support of a 1GIG Ethernet probe. Identified design issues and corrective actions for excessive transmit jitter in original design.
- Architecture and member of design team for 10GIG Ethernet probe product family shared between business units. Responsible for NEBS compliance, signal integrity, digital design and review. Also designed an integrated NEBS power system for the product.
- Design and set up of hardware design lab in the Morrisville location, and responsible for moving cellular lab from Blacksburg, VA office.
2004 - 2008 Insilica, Inc Purchased 9/2007 from Atmel Corporation Durham, NC
Systems Engineering Manager, Multimedia and Communication Division
Manage systems group and systems design activities. Implemented formal design processes and documentation control policies to improve quality of designs and manufacturing yields. Hands on experience with design and debug.
Responsible for:
- Designing and managing the design of test platforms for new ARM based devices for digital still cameras, digital photo frames, video capture, video display and audio playback applications.
- Designing and managing the design of evaluation boards and products for new ICs. The ARM based processors include interfaces for high speed video, USB 2.0, and DDR memory.
- Creating reference designs and documentation for specific customer applications.
- Board bringup and debug for initial customer designs.
- Evaluation and review of customer designs and reported problems.
- Signal integrity analysis and simulation for new ICs, reference designs, customer designs, and evaluation boards.
- Developing design guidelines for high speed interfaces, including DDR memory interfaces, DVI and HDMI video interfaces.
- Managing design interface between the Shanghai Engineering and the Durham engineering center.
2000 - 2004 Corona Networks, Inc Cary, NC
Senior Engineering Manager, ISM2 Product Development
Liaison between Alcatel and Corona Networks to migrate Corona IP services technologies to a module for Alcatel DSLAM products.
Responsible for:
- Schematic conversion and review in merging the Corona and Alcatel designs.
- Converting a Corona 2.5Gbps SAR design for compatibility with Alcatel's system.
- Defining high-speed interconnect between boards in 5 board assembly.
- Signal integrity simulations and clocking solutions and for the design.
- Concurrent to the Alcatel design efforts, responsible for maintaining, debugging, and supporting GIGE and OC48 POS interface modules, fabric, network timing, and backplane for Corona's IP services switching product line.
Senior Engineering Manager, RTP Design Center
Engineering manager responsible for the founding and staffing of the Corona Networks RTP design center. In addition to design and design management responsibilities, was responsible for recruiting, locating and outfitting office, identifying and managing design service firms as well as local assembly and rework shops. The RTP design center grew to 23 employees, and was set up to support up to 40 people.
RTP design center was responsible for high speed transport, fabric, and network timing architecture and technology for a high capacity IP services switch, the SER12000 Coordinated with engineering and manufacturing at the California headquarters on design requirements, design and build schedules, and participated as required in customer, business partner, and investor meetings. Designed a high speed 16 slot backplane utilizing 1.28Gbps interconnect technology.
Led a staff of 7 in the detailed definition of, and hands on design and debug of:
- Common processor module based on 750 PowerPC processor.
- Stratum 3 Network Timing and Alarm Module
- 36 Gbps Switching Fabric Module.
- 224 Gbps Switching Fabric Module
- OC48 POS Trunking Module.
- Other designs and test interfaces as needed to support the San Jose engineering department.
Often traveled to the California headquarters to assist in design and in the debug of critical issues with the San Jose designs.
Company expert in:
- Signal integrity and high speed design including LVDS and PECL interfaces to 2.5Gbps.
- System interconnect/UTOPIA/POS-PHY/PCI interfaces.
- System performance issues and buffering requirements.
- Maintenance and support of company?s needs for Mentor DxDesigner tools (Viewlogic), Mentor Hyperlynx signal integrity tools, Cadence OrCAD Capture schematic entry and Cadence Allegro PCB layout tools.
In supporting design, board bringup, and design verification, had hands on experience with:
- Power circuitry, high impedance signal recovery circuits, and PLL clock recovery and synchronization circuits.
- Xilinx and Altera FPGAs utilizing VHDL. Also debugged and reviewed designs in Verilog.
- Utilized many different tools to debug and test deisgns, including: Smartbits and IXIA traffic generators, Agilent and Acterna test sets, Agilent Logic analyzers, Agilent and Tektronix Osilliscopes, in-circuit emulators, microscopes, hot air reworks stations, solder equipment, etc.
1999 - 2000 Pliant Systems, Inc Formerly Broadband Technologie RTP, NC
Principal Engineer
Principal engineer for the architecture of the ATM sections in a new DLC access system.
Highlights of responsibilities:
- Identifying hardware and software architectural issues, definition of solutions, and tracking issues until resolution completed.
- Analysis of system performance.
- System architecture and requirement documentation.
1998 - 1999 Inrange Technologies, Inc Mt Laurel, NJ
Manager Technical Staff, Broadband Products
Hardware architect of a multi-service 18Gbps capacity switch, the BNX Product Line
Responsible for defining:
- Chassis structure and backplane specifications and architecture
- System controller, timing module, and fabric module.
- OC3, OC12, and OC48 ATM module architectures.
- T1/E1/DS3/E3 ATM Module and Frame Relay module architectures.
- ESCON module and Fibre Channel Module architectures.
- Developed code to test and configure hardware for fabric, OC3 and DS3 modules. This code was used by test engineering and platform software for their development efforts.
1993 - 1998 Inrange Technologies, Telenex Division Mt Laurel, NJ & Springfield, VA
Principal Member Technical Staff, Test Products
Technical representative to the ATM Forum and was the authorized voting representative.
Some of the major design accomplishments included design of an ATM OC3 module, an ATM25 interface module, and an Ethernet 10BASE-T interface for protocol analysis product . Also designed a 6-port DS3/E3 interface module for a matrix-switching product. Responsible for processor and clock synchronization, SAR interface, UTOPIA bus design, and cell/packet time stamp circuitry for a 960CF multiprocessor protocol analysis engine. Developed C code to test and configure these interfaces that was later used by test engineering and application engineering for their work
Assisted with marketing in defining target markets, features, and costs for protocol analysis products.
1988 - 1993 Softaid, Inc Columbia, MD
Technical Product Manager
Design accomplishments included the design of the majority of the company?s in-circuit emulator product lines, including hardware and firmware for the following processors: Z180/64180, 8088/86/V20/V30/V40/V50, 80C18x/18xEB/18xEC, 68000/001/302 and 68HC16. Also designed a universal emulator trace/breakpoint module that had the most advanced features at that time.
Other responsibilities included solving customer issues, visiting customer sites, and evaluating customers' designs.pan>
1984 - 1988 Computer Dynamics, Inc Greer, SC
Systems Design Engineer
Design accomplishments included designing most of the STD bus product line, including Z80, 80188 and 80186 processor based modules, NTSC video capture module, 8044 based optically isolated network controller, and diagnostic software and hardware for the all these products.
Education: